Numerous memory cell configurations are known in the art. Each possesses advantages and disadvantages, some advantages and disadvantages being related to the number of transistors employed. Skilled artisans frequently classify the various configurations into groups according to the number of transistors associated with a single storage element present in a single memory cell. Thus a circuit including a storage element coupled to but a single transistor is referred to as a 1T cell, as illustrated schematically in FIG. 1. The cell has simply a storage element, CS, and a single transistor, Q1, that functions as a transfer gate element. Applying the same taxonomy, a cell including a single storage element coupled to three transistors is referred to as a 3T cell.
Some memory cells are further classified as gain cells. These are memory cells having at least one output transistor (i.e., a gain element) configured to amplify or buffer the signal stored on the storage element, (i.e., buffering it from the output line). This permits the signal stored on the storage element to be read non-destructively, obviating the need for a write or refresh operation after each read cycle. (Note that “gain” does not necessarily require an amplification factor greater than unity.)
Interestingly, there is no conventional 2T gain cell. There is a cell configuration sometimes referred to as a 2T cell, but that configuration is actually a dual 1T cell, rather than a true 2T cell. That is, it is the circuit of FIG. 1 in duplicate, one transistor per storage element.
As noted above, gain cells are advantageous for allowing non-destructive reads. In the continual drive to make memory cells smaller and smaller, many designers strive to use fewer and fewer transistors in each gain cell. Thus, there are gain cell designs with, for example, three and four transistors known. But, as noted above, the two transistor gain cell design commonly referred to as a 2T design is not a true 2T gain cell (which would have one storage element and two transistors) but, rather, is a dual 1T cell. Despite the drive for small size and the advantages of gain cells, there is no 2T gain cell—at least not one in widespread use.
An excellent discussion of gain cells is found in Itoh, K., VLSI Memory Chip Design, Springer Series, 2001. Examples of conventional 3T gain cells described by Itoh are shown schematically in FIGS. 2–5. Each includes three transistors, Q1, Q2 and Q3, the storage element in each of these examples being the gate of Q2. The signal on the gate of Q2 is buffered at least by Q2, itself.
Memory is designed into a wide variety of systems that process a very wide variety of data. Especially in digital signal processing systems, and even more especially in systems that must process data in real time, it is desirable to have memory with plural access ports. Conventionally, adding access ports to a memory increases the complexity of the individual memory cells, for example increasing the number of transistors used in each cell, and consequently increases the power consumption of such memory.
Consequently, a need exists for a 2T gain cell suitable for use as a memory cell, for a 3T gain cell, and for other efficient gain cell designs. A further need exists for such cells which have multiple access ports and which otherwise are well-suited for digital signal processing uses including, without limitation, matrix operations such as pivots, and bit interleaving/de-interleaving.